Masayuki Hiromoto

According to our database1, Masayuki Hiromoto authored at least 48 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Improving Predicate Representation in Scene Graph Generation by Self-Supervised Learning.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

2022
SimpleZSL: Extremely Simple and Fast Zero-Shot Learning with Nearest Neighbor Classifiers.
IEICE Trans. Inf. Syst., 2022

2020
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019
GPU-based Ising computing for solving max-cut combinatorial optimization problems.
Integr., 2019

Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise.
IEEE Trans. Biomed. Eng., 2018

Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Area Efficient Annealing Processor for Ising Model without Random Number Generator.
IEICE Trans. Inf. Syst., 2018

A study on NBTI-induced delay degradation considering stress frequency dependence.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Enhancing the solution quality of hardware ising-model solver via parallel tempering.
Proceedings of the International Conference on Computer-Aided Design, 2018

Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

DWE: decrypting learning with errors with errors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2018

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

SCAM: Secured content addressable memory based on homomorphic encryption.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.
Proceedings of the 54th Annual Design Automation Conference, 2017

Efficient circuit failure probability calculation along product lifetime considering device aging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs.
IEICE Trans. Electron., 2015

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Automation of Model Parameter Estimation for Random Telegraph Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Variability in device degradations: Statistical observation of NBTI for 3996 transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array.
Proceedings of the Design, Automation and Test in Europe, 2013

2010
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features.
IEEE Trans. Circuits Syst. Video Technol., 2009

An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA.
IPSJ Trans. Syst. LSI Des. Methodol., 2009

Dynamic rate control for media streaming in high-speed mobile networks.
Proceedings of the 2009 IEEE Wireless Communications and Networking Conference, 2009

Hardware Architecture for HOG Feature Extraction.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

Cascade Classifier Using Divided CoHOG Features for Rapid Pedestrian Detection.
Proceedings of the Computer Vision Systems, 2009

Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features.
Proceedings of the 12th IEEE International Conference on Computer Vision Workshops, 2009

Hot-Swapping architecture extension for mitigation of permanent functional unit faults.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Coarse-grained dynamically reconfigurable architecture with flexible reliability.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2007
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features.
Proceedings of the 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 2007


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