Hiromitsu Awano

According to our database1, Hiromitsu Awano authored at least 29 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field.
IEICE Transactions, 2019

PUFNet: A Deep Neural Network Based Modeling Attack for Physically Unclonable Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor.
IEICE Transactions, 2018

Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

31.3 μs/Signature-Generation 256-bit 픽p ECDSA Cryptoprocessor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

RTN in Scaled Transistors for On-Chip Random Seed Generation.
IEEE Trans. VLSI Syst., 2017

Scalable Device Array for Statistical Characterization of BTI-Related Parameters.
IEEE Trans. VLSI Syst., 2017

Swarm of Sound-to-Light Conversion Devices to Monitor Acoustic Communication Among Small Nocturnal Animals.
JRM, 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.
IEICE Transactions, 2017

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation.
IEICE Transactions, 2017

Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Efficient circuit failure probability calculation along product lifetime considering device aging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling.
IEICE Transactions, 2016

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Call Alternation Between Specific Pairs of Male Frogs Revealed by a Sound-Imaging Method in Their Natural Habitat.
Proceedings of the Interspeech 2016, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Efficient transistor-level timing yield estimation via line sampling.
Proceedings of the 53rd Annual Design Automation Conference, 2016

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Recognition of In-Field Frog Chorusing Using Bayesian Nonparametric Microphone Array Processing.
Proceedings of the Computational Sustainability, 2015

Automation of Model Parameter Estimation for Random Telegraph Noise.
IEICE Transactions, 2014

Variability in device degradations: Statistical observation of NBTI for 3996 transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Multi-trap RTN parameter extraction based on Bayesian inference.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method.
IEICE Transactions, 2012

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Statistical aging under dynamic voltage scaling: A logarithmic model approach.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks.
Proceedings of the Neural Information Processing - 18th International Conference, 2011

Human-robot cooperation in arrangement of objects using confidence measure of neuro-dynamical system.
Proceedings of the IEEE International Conference on Systems, 2010