Hiromitsu Awano

Orcid: 0000-0001-9288-471X

According to our database1, Hiromitsu Awano authored at least 48 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility.
ACM Trans. Embed. Comput. Syst., October, 2023

Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation.
IEEE Robotics Autom. Lett., October, 2023

BayesianPUFNet: Training Sample Efficient Modeling Attack for Physically Unclonable Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023

B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA.
Integr., March, 2023

Pay Attention via Quantization: Enhancing Explainability of Neural Networks via Quantized Activation.
IEEE Access, 2023

DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter.
IEICE Trans. Inf. Syst., 2022

Temporal Ensemble SSDLite: Exploiting Temporal Correlation in Video for Accurate Object Detection.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Pay Attention via Binarization: Enhancing Explainability of Neural Networks via Binarization of Activation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Respiratory Rate Estimation Based on WiFi Frame Capture.
Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr., 2020

BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

PUFNet: A Deep Neural Network Based Modeling Attack for Physically Unclonable Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

31.3 μs/Signature-Generation 256-bit 픽p ECDSA Cryptoprocessor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
RTN in Scaled Transistors for On-Chip Random Seed Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Scalable Device Array for Statistical Characterization of BTI-Related Parameters.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Swarm of Sound-to-Light Conversion Devices to Monitor Acoustic Communication Among Small Nocturnal Animals.
J. Robotics Mechatronics, 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Efficient circuit failure probability calculation along product lifetime considering device aging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Variability in BTI-Induced Device Degradation: from Silicon Measurement to SRAM Yield Prediction.
PhD thesis, 2016

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Call Alternation Between Specific Pairs of Male Frogs Revealed by a Sound-Imaging Method in Their Natural Habitat.
Proceedings of the Interspeech 2016, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Efficient transistor-level timing yield estimation via line sampling.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Recognition of In-Field Frog Chorusing Using Bayesian Nonparametric Microphone Array Processing.
Proceedings of the Computational Sustainability, 2015

2014
Automation of Model Parameter Estimation for Random Telegraph Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Variability in device degradations: Statistical observation of NBTI for 3996 transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Multi-trap RTN parameter extraction based on Bayesian inference.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2012
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Statistical aging under dynamic voltage scaling: A logarithmic model approach.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks.
Proceedings of the Neural Information Processing - 18th International Conference, 2011

2010
Human-robot cooperation in arrangement of objects using confidence measure of neuro-dynamical system.
Proceedings of the IEEE International Conference on Systems, 2010


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