Michihiro Shintani

Proceedings of the IEEE International Test Conference in Asia, 2023

2022

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Systematic Unsupervised Recycled Field-Programmable Gate Array Detection.

[BibT_eX]

[DOI]

CoRR, 2022

Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression.

[BibT_eX]

[DOI]

Kyohei Shimozato

CoRR, 2022

Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

2021

Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation.

[BibT_eX]

[DOI]

Aoi Ueda

CoRR, 2021

Hardware-Software Co-Design for Decimal Multiplication.

[BibT_eX]

[DOI]

Riaz-ul-haque Mian

Comput., 2021

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Study on High-Accuracy and Low-Cost Recycled FPGA Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network.

[BibT_eX]

[DOI]

Mamoru Ishizaka

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit.

[BibT_eX]

[DOI]

Mamoru Ishizaka

J. Electron. Test., 2020

Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement.

[BibT_eX]

[DOI]

Tomoki Mino

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem.

[BibT_eX]

[DOI]

Riaz-ul-haque Mian

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Low Cost Recycled FPGA Detection Using Virtual Probe Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Artificial Neural Network Based Test Escape Screening Using Generative Model.

[BibT_eX]

[DOI]

Yoshiyuki Nakamura

Proceedings of the IEEE International Test Conference, 2018

Variation-Aware Hardware Trojan Detection through Power Side-channel.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

A study on NBTI-induced delay degradation considering stress frequency dependence.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage.

[BibT_eX]

[DOI]

Mamoru Ishizaka

Proceedings of the 27th IEEE Asian Test Symposium, 2018

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Decimal Multiplication Using Combination of Software and Hardware.

[BibT_eX]

[DOI]

Mian Riaz-ul-haque

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014

A Variability-Aware Adaptive Test Flow for Test Quality Improvement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Sensorless estimation of global device-parameters based on F<sub>max</sub> testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Device-Parameter Estimation through IDDQ Signatures.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

A Bayesian-based process parameter estimation using IDDQ current signature.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2010

Path clustering for adaptive test.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Scan based process parameter estimation through path-delay inequalities.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Small Delay Fault Model for Intra-Gate Resistive Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2007

A Variable-Length Coding Adjustable for Compressed Test Application.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

2005

Huffman-Based Test Response Coding.

[BibT_eX]

[DOI]

Hideyuki Ichihara