Toyohiko Yoshida

According to our database, Toyohiko Yoshida authored at least 12 papers between 1988 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

Code Efficiency Evaluation for Embedded Processors.

Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

Evaluation of processor code efficiency for embedded systems.

Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa

Proceedings of the 15th international conference on Supercomputing, 2001

1999

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores.

Satoshi Kumaki, Tetsuya Matsumura, Kamya Ishihara, Hiroshi Segawa, Kiyofumi Kawamoto, Hideo Ohira, Toshiaki Shimada, Hidenori Sato, Takashi Hattori, Tetsuro Wada, Hiroshi Honma, Tetsuya Watanabe, Hisakazu Sato, Ken'ichi Asano, Toyohiko Yoshida

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding.

Edgar Holmann, Toyohiko Yoshida, Akira Yamada, Shin-ichi Uramoto

J. VLSI Signal Process., 1998

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications.

Atsuo Hanami, Stefan Scotzniovsky, Kazuya Ishihara, Tetsuya Matsumura, Shin'ichi Takeuchi, Haruyuki Ohkuma, Koji Nishigaki, Hirokazu Suzuki, Masahiro Kazayama, Toyohiko Yoshida, Koji Tsuchihashi

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

A dual-issue RISC processor for multimedia signal processing.

Hisakazu Sato, Edgar Holmann, Toyohiko Yoshida, Masahito Matsuo, Toru Kengaku

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996

Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor.

Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1994

A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.

Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1991

The Gmicro/100 32-bit microprocessor.

Toyohiko Yoshida, Toru Shimisu, Shigeo Mizugaki, Jun-ichi Hinata

IEEE Micro, 1991

1990

A strategy for avoiding pipeline interlock delays in a microprocessor.

Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

A 32-bit microprocessor with high performance bit-map manipulation instructions.

Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100.

Tom Shimizu, Toyohiko Yoshida, Yuichi Saitoh, Masahito Matsuo, Tatsuya Enomoto

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988