Shunji Nakata

According to our database1, Shunji Nakata authored at least 21 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor.
J. Circuits Syst. Comput., 2017

2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current.
J. Circuits Syst. Comput., 2014

A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2012
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.
IET Circuits Devices Syst., 2012

Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system.
IET Circuits Devices Syst., 2010

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation.
IEICE Electron. Express, 2010

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Adiabatic quasi 6T-SRAM with shared writing and reading ports.
IEICE Electron. Express, 2008

2007
Electrostatic Energy, Potential Energy and Energy Dissipation for a Width-Variable Capacitor Coupled with Mechatronical Potential Energy during Adiabatic Charging.
IEICE Trans. Electron., 2007

Stability of an adiabatic circuit with inductive load using 1D-capacitor array between the power supply and ground.
IEICE Electron. Express, 2007

Stability of adiabatic circuit using asymmetric 1D-capacitor array between the power supply and ground.
IEICE Electron. Express, 2007

Stability of adiabatic reversible charging using 1D-capacitor array between the power supply and ground.
IEICE Electron. Express, 2007

2006
Adiabatic SRAM with the large margin of V<sub>th</sub> variation by the gradual change of the voltage.
IEICE Electron. Express, 2006

Analysis of the stability of adiabatic reversible logic using the theory of normal modes in coupled oscillators.
IEICE Electron. Express, 2006

2005
The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM.
IEICE Electron. Express, 2005


  Loading...