Masayuki Miyama
According to our database1,
Masayuki Miyama
authored at least 27 papers
between 2001 and 2022.
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Bibliography
2022
FPGA Implementation of 3-Bit Quantized Multi-Task CNN for Contour Detection and Disparity Estimation.
IEICE Trans. Inf. Syst., 2022
2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
2017
Proceedings of the 7th IEEE International Conference on Control System, 2017
2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current.
J. Circuits Syst. Comput., 2014
2012
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.
IET Circuits Devices Syst., 2012
2011
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Proceedings of the 2011 IEEE International Conference on Signal and Image Processing Applications, 2011
2010
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system.
IET Circuits Devices Syst., 2010
IEICE Trans. Inf. Syst., 2010
A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.
IEICE Trans. Electron., 2010
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation.
IEICE Electron. Express, 2010
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEICE Trans. Electron., 2008
A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2006
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation.
IEICE Trans. Electron., 2006
A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor.
Intell. Autom. Soft Comput., 2006
2005
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Electron., 2005
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
2004
IEEE J. Solid State Circuits, 2004
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Proceedings of the 2001 International Conference on Image Processing, 2001