Shunning Jiang

Orcid: 0000-0003-3439-5760

According to our database1, Shunning Jiang authored at least 11 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023

2021
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies.
IEEE Des. Test, 2021

UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification.
IEEE Micro, 2020

2019
PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
Mamba: closing the performance gap in productive hardware development frameworks.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
A Study of Sorting Algorithms on Approximate Memory.
Proceedings of the 2016 International Conference on Management of Data, 2016

A performance analysis framework for optimizing OpenCL applications on FPGAs.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Bank stealing for conflict mitigation in GPGPU Register File.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015


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