Cheng Tan

Orcid: 0000-0003-3727-2889

Affiliations:
  • Pacific Northwest National Laboratory, Richland, WA, US
  • Cornell University, Ithaca, NY, USA (2018 - 2020)
  • National University of Singapore, Singapore (until 2018)


According to our database1, Cheng Tan authored at least 31 papers between 2015 and 2023.

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Bibliography

2023
MPGemmFI: A Fault Injection Technique for Mixed Precision GEMM in ML Applications.
CoRR, 2023

FLASH: FPGA-Accelerated Smart Switches with GCN Case Study.
Proceedings of the 37th International Conference on Supercomputing, 2023

VecPAC: A Vectorizable and Precision-Aware CGRA.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Bridging Python to Silicon: The SODA Toolchain.
IEEE Micro, 2022

ASAP: automatic synthesis of area-efficient and precision-aware CGRAs.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

SO(DA)<sup>2</sup>: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk).
Proceedings of the 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2022

A Framework for Neural Network Inference on FPGA-Centric SmartNICs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

FCsN: A FPGA-Centric SmartNIC Framework for Neural Networks.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021
ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing.
IEEE Trans. Parallel Distributed Syst., 2021

I-GCN: A Graph Convolutional Network Accelerator with Runtime Locality Enhancement through Islandization.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Ultra-Elastic CGRAs for Irregular Loop Specialization.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing.
CoRR, 2020

OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

CQNN: a CGRA-based QNN Framework.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Synergy: An HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC.
ACM Trans. Embed. Comput. Syst., 2019

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
LOCUS: Low-Power Customizable Many-Core Architecture for Wearables.
ACM Trans. Embed. Comput. Syst., 2018

Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC.
CoRR, 2018

Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2015
Approximation-aware scheduling on heterogeneous multi-core architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015


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