Christopher Torng

According to our database, Christopher Torng authored at least 23 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina

IEEE J. Solid State Circuits, March, 2024

2023

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.

Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina

ACM Trans. Reconfigurable Technol. Syst., June, 2023

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark W. Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina

ACM Trans. Embed. Comput. Syst., March, 2023

Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays.

Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz, Christopher Torng

CoRR, 2023

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.

Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina

IEEE Comput. Archit. Lett., 2023

2022

A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion.

Kavya Sreedhar, Mark Horowitz, Christopher Torng

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.

Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina

Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.

Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions.

Kavya Sreedhar, Mark Horowitz, Christopher Torng

IACR Cryptol. ePrint Arch., 2021

Enabling Reusable Physical Design Flows with Modular Flow Generators.

Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng

CoRR, 2021

Ultra-Elastic CGRAs for Irregular Loop Specialization.

Christopher Torng, Peitian Pan, Yanghui Ou, Cheng Tan, Christopher Batten

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

Creating an Agile Hardware Design Flow.

Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks.

Cheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan, Christopher Torng, Shady Agwa, Christopher Batten

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS.

Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, Alyssa B. Apsel

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.

Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor

IEEE Micro, 2018

A modular digital VLSI flow for high-productivity SoC design.

Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.

Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016

Asymmetry-Aware Work-Stealing Runtimes.

Christopher Torng, Moyang Wang, Christopher Batten

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2014

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks.

Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B. Apsel, Christopher Batten

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013

Microarchitectural mechanisms to exploit value structure in SIMT architectures.

Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013