Christopher Torng
Orcid: 0000-0002-2385-619X
According to our database1,
Christopher Torng
authored at least 24 papers
between 2013 and 2024.
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Bibliography
2024
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits, March, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., June, 2023
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst., March, 2023
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays.
CoRR, 2023
IEEE Comput. Archit. Lett., 2023
Proceedings of the Workshop on Computer Architecture Education, 2023
2022
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IACR Cryptol. ePrint Arch., 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
2014
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013