Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator.

[BibT_eX]

[DOI]

Yongquan Shi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Big Data Security on Cloud, 2021

Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Guanghui He

Sijie Zheng

Naifeng Jing

IEEE Trans. Very Large Scale Integr. Syst., 2020

Priority Branches for Ship Detection in Optical Remote Sensing Images.

[BibT_eX]

[DOI]

Remote. Sens., 2020

Design of a Hardware Accelerator for Zero-Knowledge Proof in Blockchains.

[BibT_eX]

[DOI]

Proceedings of the Smart Computing and Communication - 5th International Conference, 2020

Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Smart Cloud, 2020

VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Identifying patch-level MSI from histological images of Colorectal Cancer by a Knowledge Distillation Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2020

A High-Throughput Tumor Location System with Deep Learning for Colorectal Cancer Histopathology Image.

[BibT_eX]

[DOI]

Proceedings of the Artificial Intelligence in Medicine, 2020

FIMIL : A high-throughput deep learning model for abnormality detection with weak annotation in microscopy images.

[BibT_eX]

[DOI]

Proceedings of the Australasian Computer Science Week, 2020

2019

A New Cellular-Based Redundant TSV Structure for Clustered Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2019

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A sharing-aware L1.5D cache for data reuse in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

CNFET-Based High Throughput SIMD Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

AXNet: approximate computing using an end-to-end trainable neural network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.

[BibT_eX]

[DOI]

Integr., 2017

Incorporating selective victim cache into GPGPU for high-performance computing.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2017

A wideband simplified transformer-based VCO with digital amplitude calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On Quality Trade-off Control for Approximate Computing Using Iterative Training.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Naifeng Jing

Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Applying Victim Cache in High Performance GPGPU Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

CNFET-based high throughput register file architecture.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

Timing-driven placement for carbon nanotube circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

CGSharing: Efficient content sharing in GPU-based cloud gaming.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Bank stealing for conflict mitigation in GPGPU Register File.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Jump test for metallic CNTs in CNFET-based SRAM.

[BibT_eX]

[DOI]

Feng Xie

Xiaoyao Liang

Qiang Xu

Krishnendu Chakrabarty

Naifeng Jing

Li Jiang

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs.

[BibT_eX]

[DOI]

Zhe Feng

Naifeng Jing

Lei He

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Compiler assisted dynamic register file in GPGPU.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Contention and energy aware mapping for real-time applications on Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011

A general statistical estimation for application mapping in Network-on-Chip.

[BibT_eX]

[DOI]

Naifeng Jing

Weifeng He

Zhigang Mao

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Statistical estimation and evaluation for communication mapping in Network-on-Chip.

[BibT_eX]

[DOI]

Integr., 2010

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.

[BibT_eX]

[DOI]

Naifeng Jing

Weifeng He

Zhigang Mao

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip.

[BibT_eX]

[DOI]

Naifeng Jing

Zhigang Mao

Yongxin Zhu

Proceedings of the International Conference on Embedded Software and Systems, 2009

Naifeng Jing

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