Naifeng Jing

According to our database1, Naifeng Jing authored at least 48 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A New Cellular-Based Redundant TSV Structure for Clustered Faults.
IEEE Trans. VLSI Syst., 2019

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.
ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. on Circuits and Systems, 2019

Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images.
IEEE Geosci. Remote Sensing Lett., 2019

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A sharing-aware L1.5D cache for data reuse in GPGPUs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.
IEEE Trans. Parallel Distrib. Syst., 2018

CNFET-Based High Throughput SIMD Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators.
CoRR, 2018

AXNet: ApproXimate computing using an end-to-end trainable neural network.
CoRR, 2018

Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.
Proceedings of the International Conference on Computer-Aided Design, 2018

AXNet: approximate computing using an end-to-end trainable neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018

A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.
IEEE Trans. VLSI Syst., 2017

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.
Integration, 2017

Incorporating selective victim cache into GPGPU for high-performance computing.
Concurrency and Computation: Practice and Experience, 2017

On Quality Trade-off Control for Approximate Computing Using Iterative Training.
Proceedings of the 54th Annual Design Automation Conference, 2017

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.
IEEE Trans. Computers, 2016

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Applying Victim Cache in High Performance GPGPU Computing.
Proceedings of the 15th International Symposium on Parallel and Distributed Computing, 2016

CNFET-based high throughput register file architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs.
TACO, 2015

Timing-driven placement for carbon nanotube circuits.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.
Proceedings of the 2015 IEEE International Test Conference, 2015

CGSharing: Efficient content sharing in GPU-based cloud gaming.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Bank stealing for conflict mitigation in GPGPU Register File.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Jump test for metallic CNTs in CNFET-based SRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs.
IEEE Trans. VLSI Syst., 2014

2013
Compiler assisted dynamic register file in GPGPU.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst., 2012

Contention and energy aware mapping for real-time applications on Network-on-Chip.
Proceedings of the International SoC Design Conference, 2012

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
A general statistical estimation for application mapping in Network-on-Chip.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Statistical estimation and evaluation for communication mapping in Network-on-Chip.
Integration, 2010

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip.
Proceedings of the International Conference on Embedded Software and Systems, 2009


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