Shreesha Srinath

According to our database, Shreesha Srinath authored at least 13 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation.

Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2018

An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware.

Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

A modular digital VLSI flow for high-productivity SoC design.

Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.

Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis.

Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.

Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Improving high-level synthesis with decoupled data structure optimization.

Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang

Proceedings of the 53rd Annual Design Automation Conference, 2016

2014

Architectural Specialization for Inter-Iteration Loop Dependence Patterns.

Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013

Design and Implementation of an "Approximate" Communication System for Wireless Media Applications.

Sayandeep Sen, Tan Zhang, Syed Gilani, Shreesha Srinath, Suman Banerjee, Sateesh Addepalli

IEEE/ACM Trans. Netw., 2013

Microarchitectural mechanisms to exploit value structure in SIMT architectures.

Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2010

Design and implementation of an "approximate" communication system for wireless media applications.

Sayandeep Sen, Syed Gilani, Shreesha Srinath, Stephen Schmitt, Suman Banerjee

Proceedings of the ACM SIGCOMM 2010 Conference on Applications, 2010

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.

Shreesha Srinath, Katherine Compton

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008

Rough Neuron Based Neural Classifier.

Ashwin Kothari, Avinash G. Keskar, Rakesh Chalasani, Shreesha Srinath

Proceedings of the First International Conference on Emerging Trends in Engineering and Technology, 2008