Sidinei Ghissoni

According to our database, Sidinei Ghissoni authored at least 9 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication.

João G. Nizer Rahmeier, Eduardo A. C. da Costa, Alessandro Girardi, Sidinei Ghissoni

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2015

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.

Sidinei Ghissoni, Eduardo Costa, Ricardo Reis

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

2014

Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors.

Sidinei Ghissoni, Eduardo A. C. da Costa, Angelo Goncalves da Luz

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2013

Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms.

Angelo Goncalves da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm.

João G. Nizer Rahmeier, Angelo G. da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

Efficient area and power multiplication part of FFT based on twiddle factor decomposition.

Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.

Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.

Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.

Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009