José Monteiro
Orcid: 0000-0003-0603-2268Affiliations:
- University of Lisbon, Portugal
- Massachusetts Institute of Technology, Cambridge, MA, USA (former, PhD 1996)
According to our database1,
José Monteiro
authored at least 114 papers
between 1993 and 2024.
Collaborative distances:
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Bibliography
2024
Parallelization Strategies for the Randomized Kaczmarz Algorithm on Large-Scale Dense Systems.
CoRR, 2024
2023
Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations.
ACM Trans. Sens. Networks, May, 2023
A Fast Monte Carlo algorithm for evaluating matrix functions with application in complex networks.
CoRR, 2023
2022
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective.
Remote. Sens., 2022
A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks.
Future Gener. Comput. Syst., 2022
Proceedings of the 9th Workshop on Accelerator Programming Using Directives, 2022
Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022
2021
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
Proceedings of the Euro-Par 2021: Parallel Processing, 2021
2020
Radix-2<sup> <i>r</i> </sup> recoding with common subexpression elimination for multiple constant multiplication.
IET Circuits Devices Syst., 2020
A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method.
Comput. Math. Appl., 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2018
WorldScientific, ISBN: 9789813238350, 2018
2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic.
Int. J. Softw. Tools Technol. Transf., 2016
A novel method for the approximation of multiplierless constant matrix vector multiplication.
EURASIP J. Embed. Syst., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Signal Process., 2015
Approximation of multiple constant multiplications using minimum look-up tables on FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Circuits Syst. Signal Process., 2014
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2014
ECHO: A novel method for the multiplierless design of constant array vector multiplication.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
ACM Trans. Design Autom. Electr. Syst., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the Model Checking Software - 20th International Symposium, 2013
Combination of radix-2<sup>m</sup> multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Exploration of tradeoffs in the design of integer cosine transforms for image compression.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications.
Integr., 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Efficient area and power multiplication part of FFT based on twiddle factor decomposition.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Finding the optimal tradeoff between area and delay in multiple constant multiplications.
Microprocess. Microsystems, 2011
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays.
J. Low Power Electron., 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Hardware implementation of a centroid-based localization algorithm for mobile sensor networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Design of low-power multiple constant multiplications using low-complexity minimum depth operations.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Optimization of gate-level area in high throughput Multiple Constant Multiplications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers.
J. Comput., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2007
A new array architecture for signed multiplication using Gray encoded radix-2<sup>m</sup> operands.
Integr., 2007
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Minimum number of operations under a general number representation for digital filter synthesis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.
Proceedings of the 43rd Design Automation Conference, 2006
2005
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Design of a radix-2<sup>m</sup> hybrid array multiplier using carry save adder format.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Integrating Dynamic Power Management in the Design Flow.
Proceedings of the VLSI: Systems on a Chip, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Sequential logic optimization for low power using input-disabling precomputation architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Integr. Comput. Aided Eng., 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
Estimation of average switching activity in combinational logic circuits using symbolic simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1996
J. VLSI Signal Process., 1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995
Optimization of combinational and sequential logic circuits for low power using precomputation.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993