Sina Arjmandpour
Orcid: 0000-0002-4587-425X
According to our database1,
Sina Arjmandpour
authored at least 6 papers
between 2022 and 2025.
Collaborative distances:
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Bibliography
2025
19.10 A 4.6GHz 63.3fs<sub>rms</sub> PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoM<sub>J</sub> Including the XO Power and Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance.
IEEE J. Solid State Circuits, April, 2024
A 0.29pJ/Step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensing in Spinal Implants Using RC Bridge.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022