Jae-Yoon Sim
Orcid: 0000-0003-1814-6211
According to our database1,
Jae-Yoon Sim
authored at least 172 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste.
IEEE J. Solid State Circuits, January, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
A Reconfigurable LDO-Assisted Physically Unclonable Function Achieving a Zero-BER With 14% Masking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
A 6.5nW, -73.5dBm Sensitivity, Cryptographic Wake-Up Receiver with a PUF-based OTP and Temperature-Insensitive Code Recovery.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 110dB-TCMRR TDM-based 8-Channel Noncontact ECG Recording IC with Suppression of Motion-Induced Coupling in PP.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
A 7-10b Programmable Cryo-CMOS TI-SAR ADC for Multichannel Qubit Readout with On-Chip Background Inter-Channel Mismatch Calibrations.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
An 18.6-$\mu $W/Ch TDM-Based 8-Channel Noncontact ECG Recording IC With Common-Mode Interference Suppression.
IEEE Trans. Biomed. Circuits Syst., December, 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Ind. Electron., 2022
An Auto-Configurable Dual-Mode MPPT for Energy Harvesting With 12 nW-180 mW Conversion Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator With an Odd Number of Inverter Stages.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An 8.9-71.3 TOPS/W Deep Learning Accelerator for Arbitrarily Quantized Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology.
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Time-Division Multiplexed 8-Channel Non-Contact ECG Recording IC with a Common-Mode Interference Tolerance of 20V<sub>PP</sub>.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 2.5-nW Radio Platform With an Internal Wake-Up Receiver for Smart Contact Lens Using a Single Loop Antenna.
IEEE J. Solid State Circuits, 2021
A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss.
IEEE Trans. Circuits Syst., 2020
Microelectron. J., 2020
A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna.
IEEE J. Solid State Circuits, 2020
IEEE Access, 2020
Proceedings of the International SoC Design Conference, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.
IEEE Trans. Biomed. Circuits Syst., 2019
Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2019
A 0.0043-mm<sup>2</sup> 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC.
IEEE J. Solid State Circuits, 2019
A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation.
IEEE J. Solid State Circuits, 2019
A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System.
IEICE Trans. Electron., 2019
A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst., 2018
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications.
IEEE J. Solid State Circuits, 2018
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.
IEEE Trans. Biomed. Circuits Syst., 2017
A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.
IEEE Trans. Biomed. Circuits Syst., 2017
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.7 A 0.0047mm<sup>2</sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement.
IEEE J. Solid State Circuits, 2016
A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC.
J. Circuits Syst. Comput., 2016
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer.
IEEE Trans. Biomed. Circuits Syst., 2015
Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array.
IEEE Trans. Biomed. Circuits Syst., 2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes.
IEEE J. Solid State Circuits, 2014
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.
IEEE J. Solid State Circuits, 2013
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS.
IEEE J. Solid State Circuits, 2013
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE J. Solid State Circuits, 2012
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.
Proceedings of the International SoC Design Conference, 2012
A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator.
Proceedings of the International SoC Design Conference, 2012
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface.
IEEE J. Solid State Circuits, 2011
J. Electr. Comput. Eng., 2011
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE J. Solid State Circuits, 2010
A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter.
IEICE Trans. Electron., 2010
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation.
IEICE Trans. Electron., 2010
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration.
IEICE Trans. Electron., 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control.
IEEE J. Solid State Circuits, 2009
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEICE Trans. Electron., 2008
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEICE Trans. Electron., 2006
2005
Multilevel differential encoding with precentering for high-speed parallel link transceiver.
IEEE J. Solid State Circuits, 2005
2004
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs.
IEEE J. Solid State Circuits, 2004
2003
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor.
IEEE J. Solid State Circuits, 2003
2002
IEEE J. Solid State Circuits, 2002
1999
IEEE J. Solid State Circuits, 1999
1997
IEEE J. Solid State Circuits, 1997