Siufu Chiu

According to our database1, Siufu Chiu authored at least 2 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2007
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.
IEEE J. Solid State Circuits, 2007

2005
A 130-nm triple-V<sub>t</sub> 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.
IEEE J. Solid State Circuits, 2005


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