Stefan Rusu

Orcid: 0000-0002-3322-9173

According to our database¹, Stefan Rusu authored at least 35 papers between 1993 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to high performance microprocessor circuit technologies".

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2020

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.

[BibT_eX]

[DOI]

Kenny Cheng-Hsiang Hsieh

IEEE J. Solid State Circuits, 2020

2019

Hot Chips 30.

[BibT_eX]

[DOI]

John Kubiatowicz

Stefan Rusu

IEEE Micro, 2019

Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC).

[BibT_eX]

[DOI]

Ángel Rodríguez-Vázquez

Kaushik Sengupta

Stefan Rusu

IEEE J. Solid State Circuits, 2019

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing.

[BibT_eX]

[DOI]

Kenny Cheng-Hsiang Hsieh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016

Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC).

[BibT_eX]

[DOI]

Andrea Mazzanti

Bram Nauta

Stefan Rusu

IEEE J. Solid State Circuits, 2016

Welcome to 2016 Hot Chips.

[BibT_eX]

[DOI]

Stefan Rusu

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[BibT_eX]

[DOI]

Stefan Rusu

Gregory Chen

IEEE J. Solid State Circuits, 2015

2014

Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC).

[BibT_eX]

[DOI]

Yann Deval

Stefan Rusu

IEEE J. Solid State Circuits, 2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

Introduction to the Special Issue on the 34th ESSCIRC.

[BibT_eX]

[DOI]

Kari A. I. Halonen

Kofi A. A. Makinwa

Stefan Rusu

IEEE J. Solid State Circuits, 2009

A 45nm 8-core enterprise Xeon® processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Multi-domain processors.

[BibT_eX]

[DOI]

Stefan Rusu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Power reduction techniques for an 8-core xeon® processor.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007).

[BibT_eX]

[DOI]

Andrea Baschirotto

Edoardo Charbon

Stefan Rusu

IEEE J. Solid State Circuits, 2008

Short Course.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Introduction to the Special Issue on ESSCIRC 2006.

[BibT_eX]

[DOI]

Andreas Kaiser

Stefan Rusu

IEEE J. Solid State Circuits, 2007

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Microprocessors.

[BibT_eX]

[DOI]

Stefan Rusu

Jim Warnock

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Introduction to the Special Issue on ESSCIRC'2004.

[BibT_eX]

[DOI]

Rolf Koch

Stefan Rusu

IEEE J. Solid State Circuits, 2005

A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

2004

Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.

[BibT_eX]

[DOI]

Stefan Rusu

Harry Muljono

Brian S. Cherkauer

IEEE Micro, 2004

Clock generation and distribution in high-performance processors.

[BibT_eX]

[DOI]

Stefan Rusu

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

A 400-MT/s 6.4-GB/s multiprocessor bus interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

A 1.5GHz third generation itanium® 2 processor.

[BibT_eX]

[DOI]

Jason Stinson

Stefan Rusu

Proceedings of the 40th Design Automation Conference, 2003

2002

Guest editorial.

[BibT_eX]

[DOI]

Christian C. Enz

Stefan Rusu

IEEE J. Solid State Circuits, 2002

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

Clock generation and distribution for the first IA-64 microprocessor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

The first IA-64 microprocessor.

[BibT_eX]

[DOI]

Stefan Rusu

Gadi Singer

IEEE J. Solid State Circuits, 2000

Itanium processor clock design.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

1993

TONIC: A timing database for VLSI design.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Stefan Rusu

Awards

IEEE Fellow

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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