Siyuan Ye
Orcid: 0009-0006-9132-4570
According to our database1,
Siyuan Ye
authored at least 19 papers
between 2021 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting.
IEEE J. Solid State Circuits, July, 2025
IEEE Trans. Circuits Syst. II Express Briefs, February, 2025
An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS.
IEEE J. Solid State Circuits, February, 2025
18.5 A Rail-to-Rail 3<sup>rd</sup>-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
LMD²F-Net: Layered Multi-Scale Dual-Branch Dual-Temporal Fusion Network for Medical Image Segmentation.
IEEE Access, 2024
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
World Wide Web (WWW), July, 2023
Heterogeneous graphlets-guided network embedding via eulerian-trail-based representation.
Inf. Sci., April, 2023
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021