Sooeun Lee

Orcid: 0000-0003-4340-3312

According to our database1, Sooeun Lee authored at least 12 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links.
IEEE J. Solid State Circuits, November, 2023

2022
A 20-Gb/s/pin 0.0024-mm<sup>2</sup> Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2018
An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching.
IEEE J. Solid State Circuits, 2018

A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement.
IEEE J. Solid State Circuits, 2016

2015
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


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