Byungsub Kim
Orcid: 0000-0003-1528-6235
According to our database1,
Byungsub Kim
authored at least 101 papers
between 2001 and 2024.
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Bibliography
2024
Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
2023
A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links.
IEEE J. Solid State Circuits, November, 2023
A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits.
Proceedings of the 20th International SoC Design Conference, 2023
2022
A Compact Single-Ended Inverter-Based Transceiver With Swing Improvement for Short-Reach Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 20-Gb/s/pin 0.0024-mm<sup>2</sup> Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 20 Gb/s/pin 1.18pJ/b 1149µm<sup>2</sup>Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
The development of a micro-pattern manufacturing method using rotating active tools with compensation of estimated errors and an LMS algorithm.
J. Intell. Manuf., 2021
2020
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss.
IEEE Trans. Circuits Syst., 2020
Microelectron. J., 2020
IEEE Access, 2020
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.
IEEE Trans. Biomed. Circuits Syst., 2019
A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation.
IEEE J. Solid State Circuits, 2019
A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Approximate Closed-Form Transfer Function Model for Multiconductor Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst., 2018
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications.
IEEE J. Solid State Circuits, 2018
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the International SoC Design Conference, 2018
Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects.
Proceedings of the International SoC Design Conference, 2018
A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.
IEEE Trans. Biomed. Circuits Syst., 2017
A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.
IEEE Trans. Biomed. Circuits Syst., 2017
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
8.7 A 0.0047mm<sup>2</sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement.
IEEE J. Solid State Circuits, 2016
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer.
IEEE Trans. Biomed. Circuits Syst., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array.
IEEE Trans. Biomed. Circuits Syst., 2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.
IEEE J. Solid State Circuits, 2013
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL.
IEEE J. Solid State Circuits, 2013
2012
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2010
IEEE J. Solid State Circuits, 2010
Int. J. Autom. Technol., 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009
2008
IEEE Des. Test Comput., 2008
2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2001
Proceedings of the American Control Conference, 2001
Proceedings of the American Control Conference, 2001