Byungsub Kim

According to our database1, Byungsub Kim authored at least 87 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

The development of a micro-pattern manufacturing method using rotating active tools with compensation of estimated errors and an LMS algorithm.
J. Intell. Manuf., 2021

2020
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Low-Power Small-Area Inverter-Based DSM for MEMS Microphone.
IEEE Trans. Circuits Syst., 2020

An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss.
IEEE Trans. Circuits Syst., 2020

A pattern-dependent injection-locked CDR for clock-embedded signaling.
Microelectron. J., 2020

A Body Channel Communication Technique Utilizing Decision Feedback Equalization.
IEEE Access, 2020

GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.
IEEE Trans. Biomed. Circuits Syst., 2019

A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation.
IEEE J. Solid State Circuits, 2019

A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Approximate Closed-Form Transfer Function Model for Multiconductor Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst., 2018

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface.
IEEE J. Solid State Circuits, 2018

An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching.
IEEE J. Solid State Circuits, 2018

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications.
IEEE J. Solid State Circuits, 2018

A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Rule-of-thumb Condition to Avoid Large HRS Current in ReRAM Crossbar Array Design.
Proceedings of the International SoC Design Conference, 2018

Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects.
Proceedings of the International SoC Design Conference, 2018

A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A low-power wide dynamic-range current readout circuit for biosensors.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Investigation on the Worst Read Scenario of a ReRAM Crossbar Array.
IEEE Trans. Very Large Scale Integr. Syst., 2017

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.
IEEE Trans. Biomed. Circuits Syst., 2017

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.
IEEE Trans. Biomed. Circuits Syst., 2017

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.7 A 0.0047mm<sup>2</sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC.
IEEE J. Solid State Circuits, 2016

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement.
IEEE J. Solid State Circuits, 2016

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface.
Proceedings of the International SoC Design Conference, 2016

All-synthesizable 6Gbps voltage-mode transmitter for serial link.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

Read margin analysis in an ReRAM crossbar array.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

A low-power LDO circuit with a fast load regulation.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer.
IEEE Trans. Biomed. Circuits Syst., 2015

An input pole tuned switching equalization scheme for high-speed serial links.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

5.7 A 29nW bandgap reference circuit.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array.
IEEE Trans. Biomed. Circuits Syst., 2014

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014

Current-Mode Transceiver for Silicon Interposer Channel.
IEEE J. Solid State Circuits, 2014

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A voltage-scalable 10-b pipelined ADC with current-mode amplifier.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.
IEEE J. Solid State Circuits, 2013

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL.
IEEE J. Solid State Circuits, 2013

2012
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2010
Equalized on-chip interconnect: modeling, analysis, and design.
PhD thesis, 2010

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels.
IEEE J. Solid State Circuits, 2010

Precision Component Technologies for Microfactory Systems Developed at KIMM.
Int. J. Autom. Technol., 2010

2009
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
IEEE J. Solid State Circuits, 2009

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

2008
Characterization of Equalized and Repeated Interconnects for NoC Applications.
IEEE Des. Test Comput., 2008

2007
Equalized interconnects for on-chip networks: modeling and optimization framework.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Power-adaptive operational amplifier with positive-feedback self biasing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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