Sören Tempel

Orcid: 0000-0002-3076-893X

According to our database1, Sören Tempel authored at least 18 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT.
IEEE Internet Things J., June, 2023

Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT.
Dataset, January, 2023

Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture.
Proceedings of the Trends in Functional Programming - 24th International Symposium, 2023

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models.
Proceedings of the Forum on Specification & Design Languages, 2023

2022
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.
Dataset, July, 2022

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware.
J. Syst. Archit., 2022

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing.
IEEE Embed. Syst. Lett., 2022

3D Visualization of Symbolic Execution Traces.
Proceedings of the Forum on Specification & Design Languages, 2022

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.
Proceedings of the Automated Technology for Verification and Analysis, 2022

Automated Detection of Spatial Memory Safety Violations for Constrained Devices.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.
Dataset, September, 2021

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.
J. Syst. Archit., 2021

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.
Proceedings of the 24th Forum on specification & Design Languages, 2021

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Mutation-based Compliance Testing for RISC-V.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
RIOT-POLICE: An implementation of spatial memory safety for the RIOT operating system.
CoRR, 2020

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020


  Loading...