Spyros Theoharis

According to our database1, Spyros Theoharis authored at least 16 papers between 1996 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2003
Power efficient data path synthesis of sum-of-products computations.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2002
Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques.
VLSI Design, 2002

Memory accesses reordering for interconnect power reduction in sum-of-products computations.
IEEE Trans. Signal Process., 2002

A fast and accurate delay dependent method for switching estimation of large combinational circuits.
J. Syst. Archit., 2002

Quantizing the 9/7 Daubechies filter coefficients for 2D DWT VLSI implementations.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

2001
A Fast and Accurate Method of Power Estimation for Logic Level Networks.
VLSI Design, 2001

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.
VLSI Design, 2001

2000
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.
Proceedings of the Integrated Circuit Design, 2000

Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions.
Proceedings of the Integrated Circuit Design, 2000

Low power synthesis of sum-of-products computation (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A methodology for the behavioral-level event-driven power management of digital receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


1999
A New Method for Low Power Design of Two-Level Logic Circuits.
VLSI Design, 1999

An efficient probabilistic method for logic circuits using real delay gate model.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1996
A novel approach for reducing the switching activity in two-level logic circuits.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Low-power design of array architectures.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996


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