Srinivas Sabbavarapu
Orcid: 0000-0003-1407-4492
According to our database1,
Srinivas Sabbavarapu
authored at least 9 papers
between 2013 and 2018.
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Bibliography
2018
J. Low Power Electron., 2018
Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction.
J. Low Power Electron., 2018
2017
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing.
J. Low Power Electron., 2017
2014
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market.
J. Low Power Electron., 2014
A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG).
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013