Steven A. Przybylski

According to our database, Steven A. Przybylski authored at least 8 papers between 1982 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe

IEEE Micro, 2016

1992

An analytical access time model for on-chip cache memories.

Tomohisa Wada, Suresh Rajan, Steven A. Przybylski

IEEE J. Solid State Circuits, August, 1992

1990

The Performance Impact of Block Sizes and Fetch Strategies.

Steven A. Przybylski

Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1989

Characteristics of Performance-Optimal Multi-Level Cache Hierarchies.

Steven A. Przybylski, Mark Horowitz, John L. Hennessy

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1988

Measurement and Evaluation of the MIPS Architecture and Processor.

Thomas R. Gross, John L. Hennessy, Steven A. Przybylski, Christopher Rowen

ACM Trans. Comput. Syst., 1988

Performance Tradeoffs in Cache Design.

Steven A. Przybylski, Mark Horowitz, John L. Hennessy

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

1986

A CMOS RISC Processor with Integrated System Functions.

John P. Moussouris, Lester M. Crudele, Danny Freitas, Craig Hansen, Ed Hudson, Roger March, Steven A. Przybylski, Tim Riordan, Chris Rowen, D. Van't Hof

Proceedings of the Spring COMPCON'86, 1986

1982

MIPS: A microprocessor architecture.

John L. Hennessy, Norman P. Jouppi, Steven A. Przybylski, Christopher Rowen, Thomas R. Gross, Forest Baskett, John Gill

Proceedings of the 15th annual workshop on Microprogramming, 1982