Michael Shebanow

According to our database, Michael Shebanow authored at least 13 papers between 1985 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.

Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe

IEEE Micro, 2016

2013

Peta Thread Computing [Keynote I].

Michael Shebanow

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2011

Improving GPU performance via large warps and two-level warp scheduling.

Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2009

Pervasive massively multithreaded GPU processors.

Michael Shebanow

Proceedings of the 6th Conference on Computing Frontiers, 2009

1995

Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor.

Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1991

Single Instruction Stream Parallelism is Greater Than Two.

Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1988

Hardware support for large atomic units in dynamically scheduled machines.

Stephen W. Melvin, Michael Shebanow, Yale N. Patt

Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

1987

Aquarius.

Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy

SIGARCH Comput. Archit. News, 1987

On tuning the microarchitecture of an HPS implementation of the VAX.

James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt

Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

1986

Run-time generation of HPS microinstructions from a VAX instruction stream.

Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen

Proceedings of the 19th annual workshop on Microprogramming, 1986

Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers.

Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei

Proceedings of the Spring COMPCON'86, 1986

1985

Critical issues regarding HPS, a high performance microarchitecture.

Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow

Proceedings of the 18th annual workshop on Microprogramming, 1985

HPS, a new microarchitecture: rationale and introduction.

Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow

Proceedings of the 18th annual workshop on Microprogramming, 1985