Subodh Kumar Singhal

Orcid: 0000-0002-1136-1421

According to our database1, Subodh Kumar Singhal authored at least 10 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An area-delay efficient single-precision floating-point multiplier for VLSI systems.
Microprocess. Microsystems, April, 2023

2021
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications.
Turkish J. Electr. Eng. Comput. Sci., 2021

2020
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
J. Circuits Syst. Comput., 2020

Area-delay and energy efficient multi-operand binary tree adder.
IET Circuits Devices Syst., 2020

2016
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic.
J. Circuits Syst. Comput., 2016

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic.
Integr., 2016

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer.
Circuits Syst. Signal Process., 2016

2012
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2009
Design of 1.3 GHz Microstrip Highpass Filter Using Optimum Distributed Short Circuited Stubs.
Proceedings of the First International Conference on Computational Intelligence, 2009

Design of 1.5 GHz Quasilumped Microstrip Highpass Filter.
Proceedings of the First International Conference on Computational Intelligence, 2009


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