Sujit Kumar Patel

According to our database, Sujit Kumar Patel authored at least 17 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Design of Frequency Sampling Rational Rate Polyphase FIR Converter.

Konudula Anjali Rao, Abhishek Kumar, Sujit Kumar Patel, Dmitry I. Kaplun, Neetesh Purohit

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023

An area-delay efficient single-precision floating-point multiplier for VLSI systems.

Anuradha, Sujit Kumar Patel, Subodh Kumar Singhal

Microprocess. Microsystems, April, 2023

Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry.

Konudula Anjali Rao, Abhishek Kumar, Dmitrii I. Kaplun, Sujit Kumar Patel, Neetesh Purohit

IET Circuits Devices Syst., January, 2023

2021

Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications.

Bharat Garg, Sujit Kumar Patel

Wirel. Pers. Commun., 2021

Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency.

Bharat Garg, Sujit Kumar Patel

J. Signal Process. Syst., 2021

Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications.

Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena

Turkish J. Electr. Eng. Comput. Sci., 2021

A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth.

Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg, Sujit Kumar Patel

Turkish J. Electr. Eng. Comput. Sci., 2021

2020

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.

Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena

J. Circuits Syst. Comput., 2020

Area-delay and energy efficient multi-operand binary tree adder.

Sujit Kumar Patel, Subodh Kumar Singhal

IET Circuits Devices Syst., 2020

An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic.

Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai

J. Electron. Test., 2020

LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing.

Bharat Garg, Sujit Kumar Patel, Sunil Dutt

J. Electron. Test., 2020

A power and area efficient approximate carry skip adder for error resilient applications.

Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai

Turkish J. Electr. Eng. Comput. Sci., 2020

2019

Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems.

Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2016

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter.

Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data.

Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Efficient very large-scale integration architecture for variable length block least mean square adaptive filter.

Basant Kumar Mohanty, Sujit Kumar Patel

IET Signal Process., 2015

2014

Area-Delay-Power Efficient Carry-Select Adder.

Basant Kumar Mohanty, Sujit Kumar Patel

IEEE Trans. Circuits Syst. II Express Briefs, 2014