Sudarshan Bahukudumbi

According to our database, Sudarshan Bahukudumbi authored at least 13 papers between 2005 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs.

Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar

IEEE Trans. Very Large Scale Integr. Syst., 2009

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2009

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

Wafer-Level Testing and Test Planning for Integrated Circuits.

Sudarshan Bahukudumbi

PhD thesis, 2008

Power-aware SoC test planning for effective utilization of port-scalable testers.

Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty

ACM Trans. Design Autom. Electr. Syst., 2008

Test-Pattern Ordering for Wafer-Level Test-During-Burn-In.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz

Proceedings of the Design, Automation and Test in Europe, 2008

Power Management for Wafer-Level Test During Burn-In.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Wafer-Level Modular Testing of Core-Based SoCs.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2007

Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.

Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs.

Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.

Sudarshan Bahukudumbi, Krishna Bharath

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005