Anuja Sehgal

According to our database, Anuja Sehgal authored at least 17 papers between 2003 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.

Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty

IEEE Trans. Computers, 2009

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.

Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick

IEEE Des. Test Comput., 2009

Test access mechanism for multiple identical cores.

Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Power-aware SoC test planning for effective utilization of port-scalable testers.

Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty

ACM Trans. Design Autom. Electr. Syst., 2008

2007

Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.

Anuja Sehgal, Krishnendu Chakrabarty

IEEE Trans. Computers, 2007

Test cost reduction for the AMD™ Athlon processor using test partitioning.

Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Test infrastructure design for mixed-signal SOCs with wrapped analog cores.

Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2006

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.

Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.

Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.

Anuja Sehgal, Krishnendu Chakrabarty

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores.

Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty

Proceedings of the 2005 Design, 2005

2004

SOC test planning using virtual test access architectures.

Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2004

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.

Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.

Anuja Sehgal, Krishnendu Chakrabarty

Proceedings of the 2004 Design, 2004

2003

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers.

Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Yield analysis for repairable embedded memories.

Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty

Proceedings of the 8th European Test Workshop, 2003

Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.

Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty

Proceedings of the 40th Design Automation Conference, 2003