Vincent John Mooney III

Affiliations:
  • Georgia Institute of Technology, Atlanta, USA


According to our database1, Vincent John Mooney III authored at least 72 papers between 1994 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Software Compilation Using FPGA Hardware: Register Allocation.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
RanCompute: Computational Security in Embedded Devices via Random Input and Output Encodings.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022

A Cryptographic Method for Defense Against MiTM Cyber Attack in the Electricity Grid Supply Chain.
Proceedings of the 2022 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2022

2021
Grid Cyber-Security Strategy in an Attacker-Defender Model.
Cryptogr., 2021

Automatic Subject Identification Using Scale-Based Ballistocardiogram Signals.
Proceedings of the Wireless Mobile Communication and Healthcare, 2021

2019
A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2018
Securing Medical Devices Against Hardware Trojan Attacks Through Analog-, Digital-, and Physiological-Based Signatures.
J. Hardw. Syst. Secur., 2018

Hardware-Based Run-Time Code Integrity in Embedded Devices.
Cryptogr., 2018

A chip-level security framework for assessing sensor data integrity: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
A novel physiological features-assisted architecture for rapidly distinguishing health problems from hardware Trojan attacks and errors in medical devices.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Use of Analog Signatures for Hardware Trojan Detection.
Proceedings of the 14th FPGAworld Conference, 2017

2015
A Novel Approach to Detect Hardware Trojan Attacks on Primary Data Inputs.
Proceedings of the 10th Workshop on Embedded Systems Security, 2015

2014
Low Power Motion Estimation Based on Probabilistic Computing.
IEEE Trans. Circuits Syst. Video Technol., 2014

A signature based architecture for Trojan detection.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013
Models for characterizing noise based PCMOS circuits.
ACM Trans. Embed. Comput. Syst., 2013

Introduction to Special Section on Probabilistic Embedded Computing.
ACM Trans. Embed. Comput. Syst., 2013

Introductions to special issue on ESWEEK 2011.
Des. Autom. Embed. Syst., 2013

2012
Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2011
Fault tolerant design for low power hierarchical search motion estimation algorithms.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Low Power Probabilistic Floating Point Multiplier Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Low Power Motion Estimation with Probabilistic Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

An approach to energy-error tradeoffs in approximate ripple carry adders.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
A More Precise Model of Noise Based PCMOS Errors.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Optimizing energy to minimize errors in dataflow graphs using approximate adders.
Proceedings of the 2010 International Conference on Compilers, 2010

2008
Task Scheduling for Control Oriented Requirements for Cyber-Physical Systems.
Proceedings of the 29th IEEE Real-Time Systems Symposium, 2008

2007
Timing analysis for preemptive multitasking real-time systems with caches.
ACM Trans. Embed. Comput. Syst., 2007

2006
Sleepy Stack Leakage Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip.
IEEE Trans. Parallel Distributed Syst., 2006

Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2005
An <i>o</i>(<i>min</i>(<i>m</i>, <i>n</i>)) parallel deadlock detection algorithm.
ACM Trans. Design Autom. Electr. Syst., 2005

Pareto Points in SRAM Design Using the Sleepy Stack Approach.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

WCRT analysis for a uniprocessor with a unified prioritized cache.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

2004
Assembly instruction level reverse execution for debugging.
ACM Trans. Softw. Eng. Methodol., 2004

Automated bus generation for multiprocessor SoC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Sleepy Stack Reduction of Leakage Power.
Proceedings of the Integrated Circuit and System Design, 2004

A Fast Assembly Level Reverse Execution Method via Dynamic Slicing.
Proceedings of the 26th International Conference on Software Engineering (ICSE 2004), 2004

Energy estimation of peripheral devices in embedded systems.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches.
Proceedings of the 2004 Design, 2004

A novel deadlock avoidance algorithm and its hardware implementation.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Golay and wavelet error control codes in VLSI.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems.
Microelectron. J., 2003

Hardware Support for Priority Inheritance.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

A Configurable Hardware Scheduler for Real-Time Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

Hardware/Software Partitioning of Operating Systems.
Proceedings of the 2003 Design, 2003

Software Streaming via Block Streaming.
Proceedings of the 2003 Design, 2003

PARLAK: Parametrized Lock Cache Generator.
Proceedings of the 2003 Design, 2003

A comparison of the RTU hardware RTOS with a hardware/software RTOS.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Hardware/Software Partitioning of Operating Systems.
Proceedings of the Embedded Software for SoC, 2003

Software Streaming via Block Streaming.
Proceedings of the Embedded Software for SoC, 2003

2002
A Hardware-Software Real-Time Operating System Framework for SoCs.
IEEE Des. Test Comput., 2002

The System-on-a-Chip Lock Cache.
Des. Autom. Embed. Syst., 2002

Instruction-level reverse execution for debugging.
Proceedings of the 2002 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis For Software Tools and Engineering, 2002

Design space optimization of embedded memory systems via data remapping.
Proceedings of the 2002 Joint Conference on Languages, 2002

Round-Robin Arbiter Design and Generation.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Hardware support for real-time embedded multiprocessor system-on-a-chip memory management.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
A Debugger RTOS for Embedded Systems.
Proceedings of the 27th EUROMICRO Conference 2001: A Net Odyssey, 2001

A Comparison of Five Different Multiprocessor SoC Bus Architectures.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

System-on-a-chip processor synchronization support in hardware.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A novel parallel deadlock detection algorithm and architecture.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

The emerging power crisis in embedded processors: what can a poor compiler do?
Proceedings of the 2001 International Conference on Compilers, 2001

A system-on-a-chip lock cache with task preemption support.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems.
Des. Autom. Embed. Syst., 2000

A dynamic memory management unit for embedded real-time system-on-a-chip.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Path-based Edge Activation for Dynamic Run-Time Scheduling.
Proceedings of the 12th International Symposium on System Synthesis, 1999

1998
System Level Design for System on a Chip.
Des. Autom. Embed. Syst., 1998

1997
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Synthesis from mixed specifications.
Proceedings of the conference on European design automation, 1996

1994
Redesigning hardware-software systems.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994


  Loading...