Scott C. Smith

Orcid: 0000-0001-9863-6637

According to our database1, Scott C. Smith authored at least 63 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits.
IEEE Access, 2023

Approximate Memory for Low-Power Video Applications.
IEEE Access, 2023

2022
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits.
IET Comput. Digit. Tech., 2022

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism.
J. Electron. Test., 2022

2021
Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT.
IEEE Internet Things J., 2021

Security Threat Modeling for Power Transformers in Cyber-Physical Environments.
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2021

2020
An Ancillary Services Model for Data Centers and Power Systems.
IEEE Trans. Cloud Comput., 2020

Performance optimization of rotation-tolerant Viola-Jones-based blackbird detection.
J. Real Time Image Process., 2020

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Formal Verification of Completion-Completeness for NCL Circuits.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Hardware Trojan Design and Detection in Asynchronous NCL Circuits.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Formal Modeling and Verification of PCHB Asynchronous Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
An FPGA-in-the-loop approach for HDL motor controller verification.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Analysis and design of CMOS resettable C-elements.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Formal modeling and verification for pre-charge half buffer gates and circuits.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Design for Testability of Sleep Convention Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

2014
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014

SCL design of a pipelined 8051 ALU.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Equivalence verification for NULL Convention Logic (NCL) circuits.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic.
Microelectron. J., 2013

An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency.
J. Low Power Electron., 2013

Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Sleep Convention Logic using partially slept function blocks.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
CMOS Implementation of Threshold Gates with Hysteresis.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

CMOS implementation of static threshold gates with hysteresis: A new approach.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

CMOS implementation comparison of NCL gates.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Uncle - An RTL Approach to Asynchronous Design.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2010
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum.
IEEE Trans. Educ., 2010

Delay-Insensitive Cell Matrix.
Proceedings of the 2010 International Conference on Computer Design, 2010

2009
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79800-9, 2009

Integrated software-hardware design for ultra-low power infrastructure monitoring.
Proceedings of the 12th International IEEE Conference on Intelligent Transportation Systems, 2009

Particle Swarm Optimization: A Hardware Implementation.
Proceedings of the 2009 International Conference on Computer Design, 2009

Delay-Insensitive Ternary Logic.
Proceedings of the 2009 International Conference on Computer Design, 2009

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power.
J. Low Power Electron., 2008

2007
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Automated energy calculation and estimation for delay-insensitive digital circuits.
Microelectron. J., 2007

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits.
Eng. Appl. Artif. Intell., 2007

Design of a logic element for implementing an asynchronous FPGA.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006
Speedup of NULL convention digital circuits using NULL cycle reduction.
J. Syst. Archit., 2006

2005
Development of a large word-width high-speed asynchronous multiply and accumulate unit.
Integr., 2005

Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation.
Proceedings of the 2005 International Conference on Computer Design, 2005

High-Speed Energy Estimation for Delay-Insensitive Circuits.
Proceedings of the 2005 International Conference on Computer Design, 2005

Implementation of Design For Test for Asynchronous NCL Designs.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
Optimization of NULL convention self-timed circuits.
Integr., 2004

Design of a NULL Convention Self-Timed Divider.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Design and Characterization of Null Convention Self-Timed Multipliers.
IEEE Des. Test Comput., 2003

Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy.
Proceedings of the International Conference on VLSI, 2003

Design and Characterization of NULL Convention Arithmetic Logic Units.
Proceedings of the International Conference on VLSI, 2003

On generating random systems: a gramian approach.
Proceedings of the American Control Conference, 2003

2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
J. Syst. Archit., 2002

Speedup of Self-Timed Digital Systems Using Early Completion.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

2001
Delay-insensitive gate-level pipelining.
Integr., 2001


  Loading...