Sukumar Jairam

According to our database1, Sukumar Jairam authored at least 11 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

2010
Clock gating approaches by IOEX graphs and cluster efficiency plots.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Clock gating effectiveness metrics: Applications to power optimization.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Techniques for Early Package Closure in System-in-Packages.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

An SSO Based Methodology for EM Emission Estimation from SoCs.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Clock gating for power optimization in ASIC design cycle theory & practice.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
A Methodology for Switching Activity Based IO Powerpad Optimisation.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004


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