Jagdish C. Rao

According to our database, Jagdish C. Rao authored at least 8 papers between 1999 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.

R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Clock gating effectiveness metrics: Applications to power optimization.

Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Clock gating for power optimization in ASIC design cycle theory & practice.

Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2006

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.

Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.

Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.

Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.

Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.

Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.

Proceedings of the IEEE International Conference On Computer Design, 1999