H. Udayakumar

According to our database1, H. Udayakumar authored at least 13 papers between 1999 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2009
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Optimization strategies to improve statistical timing.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Clock gating effectiveness metrics: Applications to power optimization.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Memory Power Modeling - A Novel Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

An SSO Based Methodology for EM Emission Estimation from SoCs.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Clock gating for power optimization in ASIC design cycle theory & practice.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2006
A Methodology for Switching Activity Based IO Powerpad Optimisation.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Package-silicon co-design - Experiment with an SOC design.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2002
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.
Proceedings of the IEEE International Conference On Computer Design, 1999


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