Sun-Il Hwang
Orcid: 0000-0002-7482-5238
According to our database1,
Sun-Il Hwang
authored at least 7 papers
between 2014 and 2018.
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Bibliography
2018
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE J. Solid State Circuits, 2017
2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs.
IEEE J. Solid State Circuits, 2016
2015
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.
IEEE J. Solid State Circuits, 2015
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014