Dong-Shin Jo

According to our database1, Dong-Shin Jo authored at least 8 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016

2015
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation.
IEEE J. Solid State Circuits, 2015

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015


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