Min-Jae Seo

According to our database1, Min-Jae Seo authored at least 14 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability.
IEEE J. Solid State Circuits, 2020

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers.
IEEE J. Solid State Circuits, 2019

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits, 2018

2017
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016

2015
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015


  Loading...