Yi-Ju Roh
Orcid: 0000-0002-0352-9407
According to our database1,
Yi-Ju Roh
authored at least 4 papers
between 2016 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision.
IEEE Trans. Circuits Syst., 2020
2019
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC.
IEEE J. Solid State Circuits, 2016