Suneui Park

According to our database, Suneui Park authored at least 12 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68.

Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi

IEEE J. Solid State Circuits, 2023

A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.

Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth.

Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector.

Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi

IEEE J. Solid State Circuits, 2022

A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator.

Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS.

Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration.

Heein Yoon, Suneui Park, Jaehyouk Choi

IEEE J. Solid State Circuits, 2019

2018

An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique.

Younghyun Lim, Jeonghyun Lee, Suneui Park, Yongwoo Jo, Jaehyouk Choi

IEEE J. Solid State Circuits, 2018

A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.

Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate.

Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate.

Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration.

Suneui Park, Heein Yoon, Jaehyouk Choi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017