Sung Min Park

Orcid: 0000-0003-2653-9955

Affiliations:
  • Ewha Womans University, Department of Electronic and Electrical Engineering, Seoul, South Korea
  • Imperial College London, UK (PhD 2000)


According to our database1, Sung Min Park authored at least 28 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
An Indoor-Monitoring LiDAR Sensor for Patients with Alzheimer Disease Residing in Long-Term Care Facilities.
Sensors, 2022

2019
A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

2014
A 3.125-to-22-Gb/s multi-rate clock and data recovery using voltage-regulated active filter.
IEICE Electron. Express, 2014

A multi-channel current-mode CMOS optical receiver array for active optical HDMI cables.
IEICE Electron. Express, 2014

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13-μm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer.
IEEE J. Solid State Circuits, 2010

An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 4Gb/s current-mode optical transceiver in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Current-mode gigabit optical receivers in submicron CMOS technologies.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Optical Communications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A 1.8V, 60dB Omega 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A 1Gb/s 4-Channel Optical Transceiver Chipset for Automotive Wired Networks.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Four-channel CMOS photoreceiver array for parallel optical interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications.
IEEE J. Solid State Circuits, 2004

1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects.
IEEE J. Solid State Circuits, 2004

Four-channel SiGe transimpedance amplifier array for parallel optical interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique.
IEEE J. Solid State Circuits, 2003

CMOS optical receiver chipset for gigabit Ethernet applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
A high-speed four-channel integrated optical receiver array using SiGe HBT technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
On the design of low-noise, giga-hertz bandwidth preamplifiers for optical receiver applications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


  Loading...