Sunil Rathore

According to our database, Sunil Rathore authored at least 11 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Novel Latch Reset Technique Enabling Sub-6µw Operation in Double-Tail Comparator.

Aditya Dubey, Sunil Rathore, Navjeet Bagga

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2024

Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET.

Sunil Rathore, Navjeet Bagga, S. Dasgupta

Proceedings of the IEEE International Reliability Physics Symposium, 2024

TG-in-DRAM: A Transmission Gate based Full Adder using Multi-row Activation for enhanced Throughput in CIM Architectures.

Sambhav Sharma, Garima Choudhary, Neha Gupta, Sunil Rathore, Anand Bulusu, Sudeb Dasgupta

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023

Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET.

Sunil Rathore, Rajeewa Kumar Jaisawal, Pravin Neminath Kondekar, Navjeet Bagga

Microelectron. J., September, 2023

Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET.

Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navneet Gandhi, Shashank Banchhor, Young Suh Song, Navjeet Bagga

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Gate Oxide Induced Reliability Assessment of Junctionless FinFET-Based Hydrogen Gas Sensor.

Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar P. Georgiev, Navjeet Bagga

Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023

2022

Investigation of geometrical impact on a P⁺ buried negative capacitance SOI FET.

Toushik Santra, Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Saheli Sarkhel, Navjeet Bagga

Microelectron. J., 2022

Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor.

Sunil Rathore, Rajeewa Kumar Jaisawal, Navneet Gandhi, P. N. Kondekar, Navjeet Bagga

Microelectron. J., 2022

Insights into the operation of negative capacitance FinFET for low power logic applications.

Rajeewa Kumar Jaisawal, P. N. Kondekar, Sameer Yadav, Pranshoo Upadhyay, Bhaskar Awadhiya, Sunil Rathore

Microelectron. J., 2022

Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α).

Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2017

Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA.

Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017