S. DasGupta

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2015
Sensitivity analysis of DRV for various configurations of SRAM.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Trapping characteristics and parametric shifts in lateral GaN HEMTs with SiO2/AlGaN gate stacks.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Sinusoidal Clocked Sense-amplifier-Based Energy Recovery flip-Flops.
J. Circuits Syst. Comput., 2014

High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013
Energy estimation for n-input Adiabatic Logic gate: a Proposed Analytical Model.
J. Circuits Syst. Comput., 2013

Picard's method to solve a system of biaffine equations and its application to pole placement.
Proceedings of the IEEE International Conference on Control Applications, 2013

2011
An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design.
J. Low Power Electron., 2011

Routing of asynchronous Clos networks.
IET Comput. Digit. Tech., 2011

2002
Exact Fuzzy Modeling and Optimal control of a Launch Vehicle in the atmospheric phase.
Proceedings of the Seventh International Conference on Control, 2002

1998
CHDStd - application support for reusable hierarchical interconnect timing views.
Proceedings of the 1998 International Symposium on Physical Design, 1998

Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel).
Proceedings of the 1998 International Symposium on Physical Design, 1998

Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis.
Proceedings of the ASP-DAC '98, 1998

1997
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1992
A Simple Model for Lindhard Continuum Potential useful for Channeling Simulation.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1990
Optimization of a digital neuron design.
Proceedings of the Proceedings 23rd Annual Simulation Symposium (ANSS-23 1990), 1990

Effect of data compression of ERP sign preprocessed by FWT algorithm upon a neural network classifier.
Proceedings of the Proceedings 23rd Annual Simulation Symposium (ANSS-23 1990), 1990

1989
Description Language for a Neural Network Architecture.
Proceedings of the Intelligent Autonomous Systems 2, 1989

Design of a general purpose meta-assembler for parallel processor environment in ISPS.
Proceedings of the Proceedings 22nd Annual Simulation Symposium (ANSS-22 1989), 1989

1987
Simulation of a computer with variable hardware and variable instruction set.
Proceedings of the Proceedings 20th Annual Simulation Symposium (ANSS-20 1987), 1987

1986
Tutorial on parallel processing for design automation applications (tutorial session).
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986


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