Suraj Mandal

Orcid: 0000-0002-2855-6559

According to our database1, Suraj Mandal authored at least 9 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
SensoPUF: Securing Sensor Data Using PUF for Lightweight Security.
IEEE Trans. Consumer Electron., May, 2026

2025
Hardware Implementation of Stealthy and Lightweight Backdoor for CRYSTALS-Kyber.
IACR Cryptol. ePrint Arch., 2025

2024
Winograd for NTT: A Case Study on Higher-Radix and Low-Latency Implementation of NTT for Post Quantum Cryptography on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT.
ACM Trans. Design Autom. Electr. Syst., 2022

2019
A Novel Test Vector Generation Method for Hardware Trojan Detection.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019


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