Debapriya Basu Roy
Orcid: 0000-0003-4664-5237
According to our database1,
Debapriya Basu Roy
authored at least 54 papers
between 2012 and 2024.
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Bibliography
2024
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Computers, 2022
Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2020
A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction.
IEEE Trans. Inf. Forensics Secur., 2020
Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks.
ACM J. Emerg. Technol. Comput. Syst., 2020
A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2020
Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the Advances in Cryptology - EUROCRYPT 2020, 2020
2019
High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves.
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
IEEE Trans. Computers, 2019
Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications.
J. Hardw. Syst. Secur., 2019
Automatic generation of HCCA-resistant scalar multiplication algorithm by proper sequencing of field multiplier operands.
J. Cryptogr. Eng., 2019
Breach the Gate: Exploiting Observability for Fault Template Attacks on Block Ciphers.
IACR Cryptol. ePrint Arch., 2019
Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs.
J. Electron. Test., 2019
CoRR, 2019
Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019
2018
J. Hardw. Syst. Secur., 2018
IEEE Embed. Syst. Lett., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p).
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the Computing Frontiers Conference, 2017
2016
Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems.
IACR Cryptol. ePrint Arch., 2016
IACR Cryptol. ePrint Arch., 2016
Exploiting Safe Error based Leakage of RFID Authentication Protocol using Hardware Trojan Horse.
IACR Cryptol. ePrint Arch., 2016
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Inner collisions in ECC: Vulnerabilities of complete addition formulas for NIST curves.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Proceedings of the 3rd ACM International Workshop on ASIA Public-Key Cryptography, 2016
2015
IACR Cryptol. ePrint Arch., 2015
ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p).
IACR Cryptol. ePrint Arch., 2015
Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance.
IACR Cryptol. ePrint Arch., 2015
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012