Takahiro Iinuma

Orcid: 0000-0001-8160-7434

According to our database1, Takahiro Iinuma authored at least 10 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Controlling Chaotic Resonance with Extremely Local-Specific Feedback Signals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2023
Extremely Weak Feedback Method for Controlling Chaotic Resonance.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2023

2022
Assembly of Echo State Networks Driven by Segregated Low Dimensional Signals.
Proceedings of the International Joint Conference on Neural Networks, 2022

2020
5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 1/4-inch 3.9Mpixel low-power event-driven back-illuminated stacked CMOS image sensor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2008
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Trans. Electron., 2008

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
Proceedings of the IFIP VLSI-SoC 2006, 2006


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