Tetsuro Matsuno

According to our database, Tetsuro Matsuno authored at least 8 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits.

Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

IEICE Trans. Electron., 2010

2009

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.

Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.

Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.

Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno

Proceedings of the IFIP VLSI-SoC 2006, 2006

2005

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.

Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.

Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Electron., 2005