Junichi Miyakoshi
Orcid: 0000-0003-2989-7619
According to our database1,
Junichi Miyakoshi
authored at least 26 papers
between 2002 and 2023.
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Bibliography
2023
IET Cyper-Phys. Syst.: Theory & Appl., March, 2023
Mixbiotic society measures: Comparison of organizational structures based on communication simulation.
CoRR, 2023
CoRR, 2023
Subjective-objective policy making approach: Coupling of resident-values multiple regression analysis with value-indices, multi-agent-based simulation.
CoRR, 2023
2013
Proceedings of the Medical Imaging 2013: Image Processing, 2013
2012
Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge term.
Proceedings of the Medical Imaging 2012: Image Processing, 2012
Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method.
Proceedings of the Medical Imaging 2012: Computer-Aided Diagnosis, 2012
2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2006
A 0.3-V Operating, <i>V</i><sub>th</sub>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.
IEICE Trans. Electron., 2006
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation.
IEICE Trans. Electron., 2006
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
Proceedings of the IFIP VLSI-SoC 2006, 2006
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Electron., 2005
2004
IEEE J. Solid State Circuits, 2004
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002