Takanori Saeki

According to our database, Takanori Saeki authored at least 4 papers between 1996 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2000

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand".

Takanori Saeki, Masafumi Mitsuishi, Hiroaki Iwaki, Mitsuaki Tagishi

IEEE J. Solid State Circuits, 2000

1999

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits.

Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki

IEEE J. Solid State Circuits, 1999

1998

The direct skew detect synchronous mirror delay (Direct SMD) for ASICs.

Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1996

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

IEEE J. Solid State Circuits, 1996