Kuniaki Koyama

According to our database1, Kuniaki Koyama authored at least 4 papers between 1995 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2003
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.
IEEE J. Solid State Circuits, 2003

2000
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
IEEE J. Solid State Circuits, 2000

1996
A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.
IEEE J. Solid State Circuits, 1996

1995
A 1-Gb DRAM for file applications.
IEEE J. Solid State Circuits, November, 1995


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