Tatsuya Matano

According to our database, Tatsuya Matano authored at least 4 papers between 1996 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

A novel on-chip voltage generator for low voltage DRAMs and PRAMs.

Tatsuya Matano, Koji Sato, Kiyoshi Nakai, Isamu Asano

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2005

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.

Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi

IEEE J. Solid State Circuits, 2005

2003

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.

Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama

IEEE J. Solid State Circuits, 2003

1996

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda

IEEE J. Solid State Circuits, 1996